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mirror of https://github.com/veracrypt/VeraCrypt.git synced 2026-06-17 01:56:10 -05:00

Fix AVX2 feature gating

AVX2 support is advertised by CPUID leaf 7, subleaf 0, EBX bit 5. The previous early assignment used cpuid1[1] bit 5, which is CPUID leaf 1 EBX and is not the AVX2 feature bit.

Record the leaf 7 AVX2 bit separately and assign g_hasAVX2 only after vendor-specific detection has completed. The final value is now gated by g_hasAVX, which reflects the OS/XCR0 AVX state check, so AVX2 code is not selected unless both the CPU and OS state support it.
This commit is contained in:
Mounir IDRASSI
2026-05-31 14:32:00 +09:00
parent 3b27eb1acf
commit 11739c41f4
+6 -4
View File
@@ -326,6 +326,7 @@ static BOOL CheckSHA256Support() {
void DetectX86Features()
{
uint32 cpuid[4] = {0}, cpuid1[4] = {0}, cpuid2[4] = {0};
int leaf7_avx2 = 0;
if (!CpuId(0, cpuid))
return;
if (!CpuId(1, cpuid1))
@@ -342,7 +343,7 @@ void DetectX86Features()
uint64 xcrFeatureMask = xgetbv();
g_hasAVX = (xcrFeatureMask & 0x6) == 0x6;
}
g_hasAVX2 = g_hasAVX && (cpuid1[1] & (1 << 5));
g_hasAVX2 = 0;
g_hasBMI2 = g_hasSSE2 && (cpuid1[1] & (1 << 8));
g_hasSSE42 = g_hasSSE2 && (cpuid1[2] & (1 << 20));
g_hasSSE41 = g_hasSSE2 && (cpuid1[2] & (1 << 19));
@@ -393,7 +394,7 @@ void DetectX86Features()
if (CpuId(7, cpuid2))
{
g_hasRDSEED = (cpuid2[1] & (1 << 18)) != 0;
g_hasAVX2 = (cpuid2[1] & (1 << 5)) != 0;
leaf7_avx2 = (cpuid2[1] & (1 << 5)) != 0;
g_hasBMI2 = (cpuid2[1] & (1 << 8)) != 0;
}
}
@@ -410,11 +411,12 @@ void DetectX86Features()
if (CpuId(7, cpuid2))
{
g_hasRDSEED = (cpuid2[1] & (1 << 18)) != 0;
g_hasAVX2 = (cpuid2[1] & (1 << 5)) != 0;
leaf7_avx2 = (cpuid2[1] & (1 << 5)) != 0;
g_hasBMI2 = (cpuid2[1] & (1 << 8)) != 0;
}
}
}
g_hasAVX2 = g_hasAVX && leaf7_avx2;
#if defined(_MSC_VER) && !defined(_UEFI)
/* Add check fur buggy RDRAND (AMD Ryzen case) even if we always use RDSEED instead of RDRAND when RDSEED available */
if (g_hasRDRAND)
@@ -537,4 +539,4 @@ void DetectArmFeatures()
g_hasSHA256ARM = CPU_QuerySHA2();
}
#endif
#endif