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https://github.com/veracrypt/VeraCrypt.git
synced 2026-06-17 01:56:10 -05:00
Fix AVX2 feature gating
AVX2 support is advertised by CPUID leaf 7, subleaf 0, EBX bit 5. The previous early assignment used cpuid1[1] bit 5, which is CPUID leaf 1 EBX and is not the AVX2 feature bit. Record the leaf 7 AVX2 bit separately and assign g_hasAVX2 only after vendor-specific detection has completed. The final value is now gated by g_hasAVX, which reflects the OS/XCR0 AVX state check, so AVX2 code is not selected unless both the CPU and OS state support it.
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+6
-4
@@ -326,6 +326,7 @@ static BOOL CheckSHA256Support() {
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void DetectX86Features()
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{
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uint32 cpuid[4] = {0}, cpuid1[4] = {0}, cpuid2[4] = {0};
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int leaf7_avx2 = 0;
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if (!CpuId(0, cpuid))
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return;
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if (!CpuId(1, cpuid1))
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@@ -342,7 +343,7 @@ void DetectX86Features()
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uint64 xcrFeatureMask = xgetbv();
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g_hasAVX = (xcrFeatureMask & 0x6) == 0x6;
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}
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g_hasAVX2 = g_hasAVX && (cpuid1[1] & (1 << 5));
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g_hasAVX2 = 0;
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g_hasBMI2 = g_hasSSE2 && (cpuid1[1] & (1 << 8));
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g_hasSSE42 = g_hasSSE2 && (cpuid1[2] & (1 << 20));
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g_hasSSE41 = g_hasSSE2 && (cpuid1[2] & (1 << 19));
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@@ -393,7 +394,7 @@ void DetectX86Features()
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if (CpuId(7, cpuid2))
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{
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g_hasRDSEED = (cpuid2[1] & (1 << 18)) != 0;
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g_hasAVX2 = (cpuid2[1] & (1 << 5)) != 0;
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leaf7_avx2 = (cpuid2[1] & (1 << 5)) != 0;
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g_hasBMI2 = (cpuid2[1] & (1 << 8)) != 0;
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}
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}
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@@ -410,11 +411,12 @@ void DetectX86Features()
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if (CpuId(7, cpuid2))
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{
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g_hasRDSEED = (cpuid2[1] & (1 << 18)) != 0;
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g_hasAVX2 = (cpuid2[1] & (1 << 5)) != 0;
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leaf7_avx2 = (cpuid2[1] & (1 << 5)) != 0;
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g_hasBMI2 = (cpuid2[1] & (1 << 8)) != 0;
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}
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}
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}
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g_hasAVX2 = g_hasAVX && leaf7_avx2;
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#if defined(_MSC_VER) && !defined(_UEFI)
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/* Add check fur buggy RDRAND (AMD Ryzen case) even if we always use RDSEED instead of RDRAND when RDSEED available */
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if (g_hasRDRAND)
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@@ -537,4 +539,4 @@ void DetectArmFeatures()
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g_hasSHA256ARM = CPU_QuerySHA2();
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}
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#endif
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#endif
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